gusucode.com > visionhdl工具箱matlab源码程序 > visionhdl/visionhdlutilities/@visionhdlsupport/@Histogram/cgireml/histFSM.m
function [resetRAM, dataAcq,readOut] = histFSM(vStartReg,vStart,vEnd,binReset,resetDone) % ********************************************** % {RAMIni, sysReady, dataAcq,readOut} % RAMIni: wake up state, takes Numbins cycle to reset, ignore all control % signals, automatically goes to Ready state when reset is complete % Ready: Goes to DataAcq when vStart ==1, goes to RAMIni when % binReset ==1 % DataAcq: stay when vStart ==1; goes to RAMIni when % binReset==1; goes to Readout when vEnd ==1 % Readout: goes to DataAcq when vStart ==1 (running % histogram);goes to RAMIni when binReset ==1; persistent histState stype = numerictype(0,2,0); resetRAM = false; dataAcq =false; readOut =false; if isempty(histState) histState = fi(0,'numerictype',stype); resetRAM = false; end switch (histState) case 0 %'RAMIini' resetRAM = true; dataAcq = false; readOut = false; %if obj.waddr == obj.binNumber if resetDone histState = fi(1,'numerictype',stype); end case 1 %Ready resetRAM = false; dataAcq = false; readOut = false; if vStartReg histState = fi(2,'numerictype',stype); dataAcq = true; elseif binReset histState = fi(0,'numerictype',stype); resetRAM = true; end case 2 %DataAcq dataAcq = true; resetRAM = false; readOut = false; if binReset histState = fi(0,'numerictype',stype); resetRAM = true; dataAcq = false; elseif vEnd histState = fi(3,'numerictype',stype); end case 3 % need to worry about delays in DataAcq resetRAM = false; dataAcq = false; readOut = true; if vStart histState = fi(2,'numerictype',stype); dataAcq = true; readOut = false; elseif binReset histState = fi(0,'numerictype',stype); resetRAM = true; readOut = false; end end